Below is a list of my most important work and research activities. More information about these activities can be provided on a request basis. This section is updated frequently to include all recent advancements in my work. However, it only includes works related to my main professional activity (as a computer engineer) that I have completed under contract or during my studies. Voluntary (or free-time) work as well as non-computer engineering activities can be found in this page.



Published Work

- Papers in Journals / Conferences / Workshops:

  • M. Rabozzi, R. Brondolin, G. Natale, E. Del Sozzo, M. Huebner, A. Brokalakis, C. Ciobanu, D. Stroobandt, M. D. Santambrogio, “A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project”, to be presented in IEEE Computer Society Annual Symposium on VLSI 2017 (ISVLSI2017), Bochum, Germany, July 2017.
  • N. Tampouratzis, A. Nikitakis, A. Brokalakis, St. Andrianakis, I. Papaefstathiou, A. Dollas, “An Open-Source Extendable, Highly-Accurate and Security Aware CPS Simulator”, International Conference on Distributed Computing in Sensor Systems 2017 (DCOSS2017), Ottawa, Canada, June 2017. [.pdf]
  • D. Stroobandt, C. B. Ciobanu, M. D. Santambrogio, G. Figueiredo, A. Brokalakis, D. Pnevmatikatos, M. Huebner, T. Becker, A. J. W. Thom, “An Open Reconfigurable Research Platform as Stepping Stone to Exascale High-Performance Computing”, Design, Automation & Test in Europe 2017 (DATE 2017), Lausanne, Switzerland, March 2017. [.pdf]
  • D. Stroobandt, A. L. Varbanescu, C. B. Ciobanu, M. Al Kadik, A. Brokalakis, G. Charitopoulos, T. Todman, X. Niu, D. Pnevmatikatos, A. Kulkarni, E. Vansteenkiste, W. Luk, M. D. Santambrogio, D. Sciuto, M. Huebner, T. Becker, G. Gaydadjiev, A. Nikitakis, A. J. W. Thom, “EXTRA: Towards the Exploitation of eXascale Technology for Reconfigurable Architectures”, 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), Tallin, June 2016. [.pdf]
  • A. Kulkarni, E. Vansteenkiste, D. Stroobandt, A. Brokalakis, A. Nikitakis, “A fully parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications”, 23rd Reconfigurable Architectures Workshop (RAW 2016), 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, Chicago, May 2016. [.pdf]
  • C. B. Ciobanu , A. L. Varbanescu, D. Pnevmatikatos, G. Charitopoulos, X. Niu , W. Luk, M. D. Santambrogio , D. Sciuto, M. Al Kadi, M. Huebner, T. Becker, G. Gaydadjiev, A. Brokalakis, A. Nikitakis, A.J. W. Thom, E. Vansteenkiste, and D. Stroobandt, “EXTRA:Towards an Efficient Open Platform for Reconfigurable High Performance Computing”, 18th IEEE International Conference on Computational Science and Engineering (CSE-2015), Porto, October 2015. [.pdf]
  • D. Pnevmatikatos, K. Papadimitriou, T. Becker, P. Böhm, A. Brokalakis, K. Bruneel, C. Ciobanu, T. Davidson, G. Gaydadjiev, K. Heyse, W. Luk, X. Niu, I. Papaefstathiou, D. Pau, O. Pell, C. Pilato, M.D. Santambrogio, D. Sciuto, D. Stroobandt, T. Todman, E. Vansteenkiste, “FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration”, Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) Journal, Available online 6 November 2014, ISSN 0141-9331, http://dx.doi.org/10.1016/j.micpro.2014.09.006 (http://www.sciencedirect.com/science/article/pii/S0141933114001409). [.pdf]
  • F. Spada, A. Scolari, G.C. Durelli, R. Cattaneo, M.D. Santambrogio, D. Sciuto, D.N. Pnevmatikatos, G.N. Gaydadjiev, O. Pell, A. Brokalakis, W. Luk, D. Stroobandt, D. Pau, “"FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board"”, 2014 IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA), Milan, Italy, 26-28 August 2014. [.pdf]
  • D. Pnevmatikatos, T. Becker, A. Brokalakis, G. Gaydadjiev, W. Luk, K. Papadimitriou, I. Papaefstathiou, O. Pell, C. Pilato, D. Pau, M. D. Santambrogio, D. Sciuto, D. Stroobandt, “Effective Reconfigurable Design: the FASTER Approach”, in Proc. 10th International Symposium on Applied Reconfigurable Computing (ARC), Vilamoura, Algarve, Portugal, Apr 14-16, 2014. [.pdf]
  • Luciano Lavagno, Mihai Lazarescu, Ioannis Papaefstathiou, Andreas Brokalakis, Johan Walters, Bart Kienhuis, Florian Schaefer, “HEAP: a Highly Efficient Adaptive multi-Processor framework”, Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) Journal, vol. 37, issue 8, pages 1050 - 1062, 17 November 2013, ISSN 0141-9331. [.pdf]
  • Dionisios Pnevmatikatos, Tobias Becker, Andreas Brokalakis, Karel Bruneel, Georgi Gaydadjiev, Wayne Luk, Kyprianos Papadimitriou, Ioannis Papaefstathiou, Oliver Pell, Christian Pilato, Mathieu Robart, Marco Santambrogio, Donatella Sciuto, Dirk Stroobandt and Tim Todman, “FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration”, 15th Euromicro Conference on Digital System Design (DSD 2012), Izmir, Turkey, September 2012. [.pdf]
  • Luciano Lavagno, Mihai Lazarescu, Johan Walters, Bart Kienhuis, Ioannis Papaefstathiou, Andreas Brokalakis, Florian Schaefer, “HEAP: a Highly Efficient Adaptive multi-Processor framework”, 15th Euromicro Conference on Digital System Design (DSD 2012), Izmir, Turkey, September 2012. [.pdf]
  • Andreas Brokalakis, Ioannis Papaefstathiou, “Using Hardware-Based Forward Error Correction to Reduce the Overall Energy Consumption of WSNs”, 2012 IEEE Wireless Communications and Networking Conference (WCNC 2012), Paris, France, April 2012. [.pdf]
  • Konstantinos Papadopoulos, Andreas Brokalakis, Ioannis Papaefstathiou, “Increasing resistance to differential power analysis attacks in reconfigurable systems”, 16th IEEE Mediterranean Electrotechnical Conference (MELECON 2012), Medina Yasmine Hammamet, Tunisia, March 2012. [.pdf]
  • Georgios Chatziparaskevas, Andreas Brokalakis, Ioannis Papaefstathiou, “An FPGA-based Parallel Processor for Black-Scholes Option Pricing Using Finite Differences Schemes”, Design, Automation & Test in Europe 2012 (DATE 2012), Dresden, Germany, March 2012. [.pdf]
  • Andreas Brokalakis, Vassilis Paliouras, “Using the Arithmetic Representation Properties of Data to Reduce the Area and Power Consumption of FFT Circuits for Wireless OFDM Systems”, IEEE Workshop on Signal Processing Systems 2011 (SiPS2011), Beirut, Lebanon, October 2011. [.pdf]
  • Andreas Brokalakis, Georgios-Grigorios Mplemenos, Konstantinos Papadopoulos, Ioannis Papaefstathiou, “RESENSE: An Innovative, Reconfigurable, Powerful and Energy Efficient WSN Node”, IEEE International Conference on Communications 2011 (ICC2011), Kyoto, Japan, June 2011. [.pdf]
  • Andreas Brokalakis, Athanasios Kakarountas, Costas Goutis, “A High-Throughput Area Efficient FPGA Implementation of AES-128 Encryption”, IEEE Workshop on Signal Processing Systems (SiPS2005), Athens, November 2005. [.pdf]

- Exhibitions / Showcases:

  • G-G. Mplemenos, K. Papadopoulos, A. Brokalakis, G. Chrysos, E. Sotiriades, I. Papaefstathiou, “RESENSE: Reconfigurable WSN Nodes”, The Second Wireless Sensing Showcase (WiSiG Showcase 09), National Physical Laboratory, July 2009, London, UK.

- Publications:

  • A. Brokalakis, "Low-power VLSI Modem Architectures for Wireless OFDM Networks: the Role of Alternative Computer Arithmetic", Master Thesis, Patras, Greece, May 2007.
  • A. Brokalakis, "Design of A Dynamic Reconfigurable RISC Processor and Implementation on an FPGA", Diploma Thesis, Patras, Greece, May 2004.

Reviewer for International Conferences / Journals

  • Reviewer for the IEEE Transactions on Wireless Communications & IEEE Transactions on Computers.
  • Reviewer for the Design, Automation and Test in Europe 2017 Conference (DATE 2017).
  • Member of the Technical Program Committee of IEEE AFRICON 2015.
  • Reviewer for the IEEE International Symposium on Circuits and Systems 2013 (ISCAS 2013).
  • Reviewer for the International Conference on Field Programmable Logic and Applications 2012 (FPL 2012).
  • Reviewer for the Communication Theory Symposium of the IEEE Global Communications Conference 2010 (GLOBECOM 2010).

EU Research Projects


Other Research Projects

  • FPGA accelerator for a financial application (Option Pricing). (employed by Telecommunication Systems Institute)

Work Projects

  • Linux server administration - Microprocessor and Hardware Laboratory, School of Electronics and Computer Engineering, Technical University of Crete
  • Bluetooth Proximity Advertising Application.
  • Record of the wireless network at the area of the Municipality of Chania for the research project “Added-value Services Based on Position for wireless Broadband Networks”, Institute for the Management of Information Systems of the Research and Innovation Centre in Information, Communication and Knowledge Technologies "Athena".
  • Design and implementation of the personal website of the photographer Rainer Pawellek.
    ( http://perso.orange.fr/rainer.pawellek/ )

Teaching Experience

  • Lab Assistant for the course "Embedded Systems" (7th semester course of the School of Electronic and Computer Engineering, Technical University of Crete).
  • Lab Assistant for the course "Computer Architecture" (8th semester course of the School of Electronic and Computer Engineering, Technical University of Crete).
  • Supervisor of the Computer Architecture Lab – 4th semester course of the Computer Engineering and Informatics Dept., University of Patras).
  • Supervisor of the Basic Electronics Lab – 3rd semester course of the Computer Engineering and Informatics Dept., University of Patras).
[Sleeker_special_clear]